Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and a thin oxide liner is thermally grown on the trench walls. The trench is then refilled with a thick insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor. The quality and thickness of the gate oxide are crucial to the performance of the finished device. After implantation of the substrate is completed, titanium silicide is formed on the gates and source/drain regions to reduce sheet resistance in these areas. Silicide formation is followed by local interconnect (LI) formation, comprising depositing, masking and etching a dielectric layer, then filling in the etched areas with a metal conductor to provide local connections between gates and active areas.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to, inter alia, control the silicon-silicon dioxide interface quality and to round the trench corner. The trench is then refilled with an insulating material (or "trench fill"), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP) using the nitride layer as a polish stop. In subsequent operations, the nitride and pad oxide are stripped off, and a gate oxide layer is grown on the exposed silicon of the substrate.
Disadvantageously, the gate oxide layer typically does not grow uniformly. Rather, it tends to be thinner at the trench edges, because the gate oxide growth rate is smaller there due to the sharpness of the trench edges and the different crystallographic orientation of the silicon at the trench edges. The thinness of the gate oxide and the sharpness of the trench edges increase the electric field strength at the trench edges, decreasing device reliability.
Furthermore, during post-gate processing, such as during the LI dielectric etching step, the field oxide at the trench edge (i.e., the interface of the substrate and the oxide) is eroded, or "gouged" by the etchant. FIG. 1A shows the substrate 1, field oxide 2, and silicide layer 4. Oxide loss at the trench edge is problematic, particularly with respect to impurities implanted close to the upper surface of the substrate 1 to form junctions. The depth d of such a junction 3 is referenced to the upper surface 1 a of the substrate 1 when the junction 3 is formed. The junction 3 follows the contour of the upper surface la of the substrate, so that the upper surface 1 a and the junction 3 are a constant distance d apart.
Thus, any subsequent oxide loss will reduce the distance between a portion of the junction 3 and the upper surface la of the substrate 1. This is illustrated in FIG. 1B, where the original oxide surface 2.sub.0 has been eroded as shown by the arrows to a lower level 2.sub.i. As a result, portion 3a of the junction 3 is closer to the upper surface of the substrate (i.e., at depth d') than it was prior to the unintended oxide removal. This unwanted oxide removal and resultant proximity of the junction to the surface 1b causes problems, such as junction leakage and junction short circuits when metal LI layer 5 is formed over the field oxide 2, thereby adversely affecting device performance.
There exists a continuing need for shallow trench isolation methodology wherein the resulting gate oxide layer at the trench edges exhibits high reliability, and wherein oxide loss at the edges of isolation trenches during post gate processing is minimized, thereby reducing junction leakage and short circuits.